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agilent HSDL-7002 irda ? ? ? ? ? 3/16 encode/decode integrated circuit in qfn package data sheet description the HSDL-7002 modulates and demodulates electrical pulses from hsdl-3201 irda ? transceiver module and other irda ? compliant transceivers. the HSDL-7002 can be used with a microcontroller/ microprocessor that has a serial communication interface (uart). prior to communication, the processor selects the transmission baud rate. serial data is then transmitted or received at the prescribed data rate. the HSDL-7002 consists or two state machines ? the sir (serial infrared) encode and sir decode blocks. it also contains a sequential block clock divide that synthesizes the required internal signal. the HSDL-7002 can be placed into the internal clock mode or external clock mode. an external crystal is needed for the internal clock mode. in applications where the external 16xclk signal is provided, a crystal is not needed. there are two data transmission modes. data can be transmitter and received in either a standard 3/16 modulation mode or a 1.63 s pulse mode. features fully compliant to irda ? physical layer specification 1.4 from 9.6 kbit/s to 115.2 kbit/s (sir) interfaces with irda ? compliant ir transceiver miniature module size with 16- pin quad-flat-no lead (qfn) package height : 0.8 mm length : 4.0 mm depth : 4.0 mm used in conjunction with standard 16550 uart transmits/receives either 1.63 s or 3/16 pulse mode internal or external clock mode programmable baud rate 2.7 ? 5.5 v operation lead free and green product applications interfaces with irda ? transceiver in: telecom applications: mobile phones modems pagers fax machines computer applications: notebook computers desktop pcs dongles or other rs-232 adapters pdas printers handheld data collection: industrial medical transportation figure 1. block diagram of HSDL-7002 sir encode sir decode clock divide /txd /nrst /ir_rxd HSDL-7002 ir_txd a0 a1 a2 16xclk pulsemod clk_sel rxd
2 order information figure 2. HSDL-7002 pin configuration part number packaging type quantity HSDL-7002 tape and reel 2500 i/o pins configuration table marking information the unit is marked with a7002 and ?yyww? on the chip. yy = year ww = work week note: there are two methods of putting the internal oscillator cell in powerdown mode. whenever the clk_sel pin is asserted high (ext ernal clock select) the oscillator is automatically put in powerdown mode, or whenever the powerdn pin asserted high. pin name type function 1 txd digital in negative edge triggered input signal that is normally tied to the sout signal of the uart (serial data to be transmitted). data is modulated and output as ir_txd. 2 rxd digital out output signal normally tied to sin signal of a uart (received serial data). rxd is the demodulated output of ir_rxd. 3 a0 digital in clock multiplex signal 4 a1 digital in clock multiplex signal 5 a2 digital in clock multiplex signal 6 clk_sel digital in used to activate either the internal or external clock. a high on this line activated the external clock (16xclk) and a low activates the internal clock. when the external clock is activated, the internal oscillator is put in powerdn mode. 7 gnd chip ground 8 nrst digital in activate low signal used to reset the irda ? sir encode & decode state machine. this signal can be tied to por (power-on-reset) or vcc. 9 ir_rxd digital in input from sir optoelectronics. input signal is a 3/16th or 1.63 s pulse that is demodulated to generate rxd output signal. 10 ir_txd digital out this is the modulated txd signal. 11 pulsemod digital in (with pull down) a high level on this input put the chip into the monoshot transmit mode. in this mode, when there is a negative transition on the txd input, a rising edge on the internal transmit modulation state machine will activate a high pulse on ir_txd for 6 crystal clock cycles. with a 3.6864 mhz crystal, this corresponds to 1.63 s. this mode cannot be used in conjunction with the 16xclk clock. it is meant to be used with the external crystal clock. by default, this input pin is pulled to gnd 12 powerdn digital in (with pull down) a high on this input put only the internal oscillator cell in powerdn mode. the cell is normally not powered down. 13 oscout analog out oscillator output 14 oscin analog in oscillator input 15 vcc power 16 16xclk digital in positive edge triggered input clock that is set to 16 times the data transmission baud rate. the encode and decode schemes require this signal. the signal is usually tied to a uart's baudout signal. the 16xclk may be provided by application circuitry if baudout is not available. this signal is required when the internal clock is not used. pin #1 corner pin 16 pin 12 pin 11 pin 10 pin 9 pin 4 pin 3 pin 2 pin 1 pin 5 pin 6 pin 7 pin 8 pin 15 pin 14 pin 13
3 absolute maximum ratings switching specifications (vcc = 2.7 to 5.5 v, t a = -20 to +85c) notes: 1. propagation delay time in the output buffer is the time taken from the input passing vcc/2 to the time of the output reaching vcc/2 with 50 pf as the output load. 2. the ouput rise time is the time taken for the outputs (rxd, ir_txd) to rise from 10% of the original value to 90% of the fina l value. 3. the output fall time is the time taken for the outputs (rxd, ir_txd) to fall from 90% of the original value to 10% of the fin al value. parameter symbol min. max. units storage temperature t s -65 +150 c operating temperature t a -40 +85 c output current i o -20 15 ma power dissipation [1] p max 0.46 w input/output voltage [2] v i /v o -0.5 vcc+0.5 v power supply voltage v cc -0.5 7.0 v electrostatic protection v esd 4000 v note: 1. all pins are protected from damage to static discharge by internal diode clamps to vcc and gnd. parameter symbol min. typ. max. units conditions propagation delay time [1] t pd 45 ns output rise time [2] t rise 13 6 22 11 24 12 ns v cc = 2.7 v, c l = 50 pf vcc = 5.5 v, c l = 50 pf output fall time [3] t fall 12 5 14 10 16 11 ns v cc = 2.7 v, c l = 50 pf v cc = 5.5 v, c l = 50 pf output capacitance on output pads used for simulation c out 50 pf
4 recommended operating conditions (vcc = 2.7 to 5.5 v, t a = -20 to +85 c) notes: 1. irda ? parameter. the max clk frequency represents the maximum clock frequency to drive the HSDL-7002?s internal state machine. under normal circumstances, the clock input should not exceed 16*115.2 kbit/s or 1.8432 mhz. this product can operate at higher clock rates, but the above is the recommended rate. 2. the maximum pulse width (t mpw ) represents the minimum pulse width of the encoded ir_txd pulse (and the ir_rxd pulse). as per the irda ? physical layer specification 1.4, the minimum pulse of the ir_txd and ir_rxd pulses should be 3*(1/1.8432 mhz) or 1.63 s. parameter symbol min. typ. max. units conditions supply voltage v cc 2.7 5.0 5.5 v input voltage v i 0v cc v ambient temperature t a -20 +85 c high level input voltage v ih 0.7 v cc v cc v low level input voltage v il 00.3 v cc v output high voltage v oh 2.6 v v cc = 2.7 v i oh = 2 ma output low voltage v ol 0.1 v v cc = 2.7 v i ol = 2 ma output high voltage v oh 5.1 v v cc = 5.5 v i oh = 2 ma output low voltage v ol 0.1 v v cc = 2.7 v i ol = 2 ma static power dissipation p stat 0.61 mw dynamic power dissipation p dyn 16.5 mw static current consumption i stat 50 100 a v cc = 2.7 v v cc = 5.5 v dynamic current consumption i dyn 1.08 2.45 3 3 ma v cc = 2.7 v v cc = 5.5 v max clk frequency (16xclk) [1] f16xclk 2 mhz minimum pulse width (ir_txd) [2] tmpw 1628 ns pulse width on monoshot (ir_txd and ir_rxd) tmpw 1628 ns value of pulldown resistor used on powerdn & pulsemod input pins rdwn 400 213 460 237 510 260 k ? v cc = 2.7 v v cc = 5.5 v trigger low level input voltage (for nrst input pin) vil_trig 0.93 2.11 0.96 2.14 0.98 2.15 vv cc = 2.7 v v cc = 5.5 v trigger high level input voltage (for nrst input pin) vih_trig 1.68 3.22 1.69 3.23 1.70 3.25 vv cc = 2.7 v v cc = 5.5 v
5 HSDL-7002 package dimensions pin assignment pin 1 /txd pin 9 /ir_rxd pin 2 rxd pin 10 ir_txd pin 3 a0 pin 11 pulsemod pin 4 a1 pin 12 powerdn pin 5 a2 pin 13 oscout pin 6 clk_sel pin 14 oscin pin 7 gnd pin 15 vcc pin 8 /nrst pin 16 16xclk nb d2 e2 e l jedec min. nom. max. min. nom. max. min. nom. max. min. nom. max. 16l 0.25 0.28 0.33 2.05 2.10 2.15 2.05 2.10 2.15 0.650 bsc. 0.55 0.60 0.65 mo-220vggc symbol dimension in mm dimension in inch minimum nominal maximum minimum nominal maximum a - 0.80 0.84 - 0.031 0.033 a1 0.00 0.02 0.04 0.00 0.0008 0.0015 a3 0.20 ref. 0.008 ref. d 3.85 4.00 4.15 0.152 0.157 0.163 e 3.85 4.00 4.15 0.152 0.157 0.163 jedec mo-220 figure 3. HSDL-7002 package dimensions
6 HSDL-7002 tape dimensions HSDL-7002 reel dimensions unit: mm label detail a "b" 330 80 quantity 2500 "c" ? 13.0 0.5 2.0 0.5 21 0.8 r1.0 detail a 2.0 0.5 16.4 +2 0 bc
7 recommended storage conditions HSDL-7002 moisture proof packaging all HSDL-7002 options are shipped in moisture proof package. once opened, moisture absorption begins. this part is compliant to jedec msl (moisture sensetive level ) 3. baking conditions if the parts are not stored in dry conditions, they must be baked before reflow to prevent damage to the parts. package temp time in reels 60 c 48hours in bulk 100 c 4hours 125 c 2 hours 150 c 1 hour time from unsealing to soldering after removal from the bag, the parts should be soldered within three days if stored at the recommended storage conditions. if times longer than three days are needed, the parts must be stored in a dry box. storage temperature 10c to 30c relative humidity below 60% rh baking should only be done once. figure 4. baking conditions chart environment less than 25 deg c, and less than 60% rh yes no no yes perform recommended baking conditions package is opened (unsealed) units in a sealed moisture-proof package no baking is necessary package is opened for less than 168 hours
8 the reflow profile is a straight-line representation of a nominal temperature profile for a convective reflow solder process. the temperature profile is divided into four process zones, each with different dt/dtime temperature change rates. the dt/dtime rates are detailed in the above table. the temperatures are measured at the component to printed circuit board connections. in process zone p1 , the pc board and HSDL-7002 castellation pins are heated to a temperature of 160c to activate the flux in the solder paste. the temperature ramp up rate, r1, is limited to 4c per second to allow for even heating of both the pc board and HSDL-7002 castellations. process zone p2 should be of sufficient time duration (60 to 120 seconds) to dry the solder paste. the temperature is raised to a level just below the liquidus point of the solder, usually 200c (392f). process zone p3 is the solder reflow zone. in zone p3, the temperature is quickly raised above the liquidus point of solder to 255c (491f) for optimum results. the dwell time above the liquidus point of solder should be between 20 and 60 seconds. it usually takes about 20 seconds to assure proper coalescing of the solder balls into liquid solder and the formation of good solder connections. beyond a dwell time of 60 seconds, the intermetallic growth within the solder connections becomes excessive, resulting in the formation of weak and unreliable connections. the temperature is then rapidly reduced to a point below the solidus temperature of the solder, usually 200c (392f), to allow the solder within the connections to freeze solid. process zone p4 is the cool down after solder freeze. the cool down rate, r5, from the liquidus point of the solder to 25c (77f) should not exceed 6c per second maximum. this limitation is necessary to allow the pc board and HSDL-7002 castellations to change dimensions evenly, putting minimal stresses on the hsdl- 7002 endec. 50 100 150 200 250 300 t-time (seconds) 25 80 120 160 180 200 230 255 0 t - temperature (?c) r1 r2 r3 r4 r5 220 max 260c 60 sec max above 220 c p1 heat up p2 solder paste dry p3 solder reflow p4 cool down recommended reflow profile process zone symbol ? t maximum ? t/ ? time heat up p1, r1 25c to 160c 4c/s solder paste dry p2, r2 160c to 200c 0.5c/s solder reflow p3, r3p3, r4 200c to 255c (260c at 10 seconds max) 255c to 200c 4c/s-6c/s cool down p4, r5 200c to 25c -6c/s
9 appendix a: general application guide for the HSDL-7002 application circuits for HSDL-7002 figure 5. HSDL-7002 connection between a standard 16550 uart and hsdl-3201 figure 6. HSDL-7002 connection between a microcontroller and hsdl-3201 rxd txd rxd ir_txd ir_rxd txd 16xclk rxd sout baudout sin nrst 10 k ? 0.1 uf vcc hsdl-3201 HSDL-7002 uart 16550 rxd txd rxd ir_txd ir_rxd txd powerdn rxd sd0 io1 sd1 nrst 10 k 0.1 uf vcc hsdl-3201 HSDL-7002 micro controller io2 io3 io4 io5 io6 a0 a1 a2 clk_sel pulsemod oscin oscout 10 m f = 3.6864 mhz 15 pf 15 pf note: powerdn can be used as a basi c chip select. th e HSDL-7002 will not be able to receive or transmit data while powerdn is asserted. selection of internal clock rate from crystal oscillator selected clock rate (bps) a2 a1 a0 crystal freq. division 115200 0 0 0 divided by 2 57600 0 0 1 divided by 4 19200 0 1 0 divided by 12 9600 0 1 1 divided by 24 38400 1 0 0 divided by 6 4800 1 0 1 divided by 48 2400 1 1 0 divided by 96
encoding scheme the encoding scheme relies on a clock being present, which is set to 16 times the data transmission baud rate (16xclk). the encoder sends a pulse for every space or ?0? that is sent on the txd line. on a high to low transition of the txd line, the generation of the pulse is delayed for 7 clock cycles of the 16xclk before the pulse is set high for 3 clock cycles (or 3/16th of a bit time) and then subsequently pulled low. this generates a 3/16th bit time pulse centered around the bit of information (?0?) that is being transmitted. for consecutive spaces, pulses with a 1 bit time delay are generated in series. if a logic ?1? (mark) is sent then the encoder does not generate a pulse. decoding scheme the irda ? -sir decoding modulation method can be thought of as a pulse- stretching scheme. every high to low transition of the ir_rxd line signifies the arrival of a pulse. this pulse needs to be stretched to accommodate 1 bit time (or 16 16xclk cycles). every pulse that is received is translated into a ?0? or space on the rxd line equal to 1 bit time. figure 7. HSDL-7002 encoding scheme figure 8. HSDL-7002 decoding scheme notes: 1. the stretched pulse must be at least ? of a bit time in duration to be correctly interpreted by a uart. 2. it is recommended that the txd remains high when not transmitting. this ensures the led is off and will not interfere with signal reception. rxd irrxd 16xclk 16 cycles 16 cycles 16 cycles 16 cycles 3 cs irtxd txd 16xclk 16 cycles 16 cycles 16 cycles 16 cycles 7 cs 3 cs
1234567891011121314151617181920212223242526 crystal clk int clk (div by 2) txd internal irtxd output irtxd (monoshot) 6 crystal cycles the figure above illustrates the operation of the monoshot when the internal clock is set to divide by 2 mode, i.e., when a2=0, a1=0, and a0=0. a rising edge on the internal modulation state machine (ir_txd output), will cause the output on the ir_txd to go up for 6 crystal clock cycles. with a 3.6864 mhz clock, this corresponds to a pulse of 1.63 s. the duration of this pulse is independent of the code a2, a1, a0 and is always 6 clock cycles of the crystal, corresponding to the monoshot operation. monoshot operation
www.agilent.com/ semiconductors for product information and a complete list of distributors, please go to our web site. for technical assistance call: americas/canada: +1 (800) 235-0312 or (408) 654-8675 europe: +49 (0) 6441 92460 china: 10800 650 0017 hong kong: (+65) 6756 2394 india, australia, new zealand: (+65) 6755 1939 japan: (+81 3) 3335-8152(domestic/inter- national), or 0120-61-1280(domestic only) korea: (+65) 6755 1989 singapore, malaysia, vietnam, thailand, philippines, indonesia: (+65) 6755 2044 taiwan: (+65) 6755 1843 data subject to change. copyright ? 2004 agilent technologies, inc. december 20, 2004 5989-1319en

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